1. FIELD OF THE INVENTION
The present invention relates to a signal read-out apparatus for a solid-state imager in which CCDs (Charge-Coupled Device) or CPDs (Charge Priming Device) are employed.
2. DESCRIPTION OF THE RELATED ART
FIG. 1 of the accompanying drawings is a view for illustrating the principle of a hitherto known CCD solid-state imager which includes a light sensitive portion 9 composed of photodiodes 2 arrayed in a matrix-like configuration, vertical CCDs 11, 12, . . . , 1N and a horizontal CCD 3 for reading out light signal charges stored in the photodiodes 2, and an amplifier 4 for amplifying the signal charges transferred thereto for outputting corresponding signals. For particulars, reference may be made to Japanese Patent Application Laid-Open No. 143479/1984 (JP-A-59-143479).
FIG. 2 of the accompanying drawings is a view showing a typical circuit arrangement of the output amplifier 4 of the solid-state imager shown in FIG. 1. In FIG. 2, a reference numeral 36 denotes a MOS-type FET which serves to transfer the signal charge Q.sub.S from the horizontal CCD 3 to a capacitor 30 which converts the signal charge Q.sub.S transferred through the horizontal CCD 3 to a corresponding voltage. The capacitor 30 has a small electrostatic capacitance C.sub.o. A reference numeral 31 denotes a MOS-type FET serving as a source follower for outputting with a low impedance a signal voltage V.sub.o (=Q.sub.S /C.sub.o) which is produced in proportion to the signal charge Q.sub.S transferred to the capacitor 30. A MOS-type FET 32 serves as a resetting MOS-FET for removing externally the signal charge Q.sub.S stored in the capacitor 30. The output signal from the MOS-FET 31 is extracted through an output terminal 33 to be applied to a load resistor 35. A capacitor 34 represents a parasitic capacitance.
Next, signal read-out operation of the device shown in FIGS. 1 and 2 will be described by referring to FIG. 3. The signal charges stored in the photodiodes 2 during a single frame period are transferred to the vertical CCDs 11, 12, . . . , 1N during a vertical retrace period. The vertical CCDs transfer the signal charges corresponding to a horizontal line during each horizontal retrace period sequentially to the horizontal CCD 3. The signal charges sequentially transferred to the horizontal CCD 3 during the horizontal retrace period are sequentially transferred to the capacitor 30 under the timing of a horizontal scanning clock pulse signal .phi..sub.H applied to the horizontal CCD 3 during a succeeding horizontal period. A signal charge Q.sub.Sl2 transferred to the capactor 30 in response to the l2-th signal transfer pulse .phi..sub.H2 causes the capacitor 30 to produce a voltage V.sub.ol2. Outputted from the ouput of the source-follower MOS-FET 31 is a hold pulse of the voltage V.sub.ol2 which is of a waveform 4l2 shown in FIG. 3. Subsequently, the signal charge Q.sub.Sl2 is removed externally through the resetting MOS-FET 32. Similarly, the next signal charge Q.sub.Sl3 is transferred to the capacitor 30 in response to the succeeding l3-th signal transfer pulse .phi..sub.H2, whereby the hold pulse of a voltage V.sub.0l3 having an output waveform 4l3 shown in FIG. 3 is outputted. Through repetition of the similar operation, the voltages V.sub.o proportional to the signal charges Q.sub.S can be outputted in the form of the pulse train having an output waveform V.sub.o. Modulated signal components of the output waveform V.sub.o shown in FIG. 3 can be extracted through a low-pass filter (LPF).
In connection with the circuit shown in FIG. 2, it should be mentioned that the resetting MOS-FET 32 is not an ideal switch element because it presents resistance in the conducting or ON state. (This resistance will be hereinafter referred to as the ON resistance). Consequently, when the resetting MOS-FET 32 is in the ON state, noise voltage due to thermal noise caused by the ON resistance of the MOS-type FET 32 in the ON state is superposed on the output voltage of the capacitor 30. When the resetting MOS-FET 32 is turned off, the instantaneous value of the abovementioned noise voltage is held to be admixed to the output signal. This phenomenon will be elucidated by referring to FIG. 4 in which a numeral 61 designates a noise voltage produced in the capacitor 30 due to the thermal noise attributable to the thermal noise of the resetting MOS-FET 32 in the ON state thereof, and a numeral 62 designates a noise waveform generated due to the noise voltage held at the instant the resetting MOS-FET 32 is turned off. As will be seen in FIG. 4, the noise voltage appears in both the positive and negative directions with equal probability. The main value of the noise voltage is small and gives rise to substantially no problem at this time point. However, since the noise voltage 62 as held (hereinafter referred to as the reset noise voltage) corresponds to the instantaneous value of the noise voltage designated by 61, the former is superposed on the output waveform and becomes a very significant noise signal.
FIG. 5 of the accompanying drawings is a view showing a hitherto known signal read-out apparatus arranged so as to eliminate the reset noise mentioned above. Referring to FIG. 5, a solid-state imager 7 shown therein is similar to the one shown in FIG. 1 in respect to the general arrangement. Accordingly, only the horizontal CCD 3 and the output amplifier 4 are shown in FIG. 5. In this apparatus, elimination of the reset noise is effected by a clamp circuit 51. Concerning this clamp circuit, description may be found in White et al's article entitled "Characterization of Surface Channel CCD Image Arrays at Low Light Levels", IEEE Journal of Solid-State Circuits, Vol. SC-9, No. 1, February 1974.
Operation of the clamp circuit 51 shown in FIG. 5 will be described by referring to waveform diagrams shown in FIG. 6 of the accompanying drawings. It is to be noted that the output waveform V.sub.o shown in FIG. 6 is the same as the output waveform V.sub.o shown in FIG. 4. The output waveform V.sub.o of the solid-state imager 7 is first supplied to the clamp circuit 51. In response to a clamp pulse .phi..sub.c, the clamp circuit 51 clamps the output waveform V.sub.o during a period in which only the reset noise 62 is contained. Thus, an output waveform V.sub.o ' from which the reset noise 62 has been eliminated is outputted from the clamp circuit. Modulated signal components of the output waveform V.sub.o ' are extracted through a low-pass filter 52. Subsequently, the modulated signal components are processed by a video signal processing circuit 53, whereby a video signal free of the reset noise can be finally obtained as the output signal.
As will be appreciated from the above description, although consideration has heretofore been paid to the influence of the reset noise, no measurements have been heretofore taken for disposing of white random noise produced by the thermal noise source constituted by the MOS-FET 31 shown in FIG. 2. Consequently, the actual output signal of the solid-state imager assumes an output waveform V.sub.o which corresponds to the superposition of the white random noise on the output waveform V.sub.o ' shown in FIG. 6.
Such being the circumstances, the clamp circuit 51 shown in FIG. 5 holds the thermal noise voltage of the source follower MOS-FET 31 (as indicated by 64 in FIG. 6), as a result of which the noise level is increased, whereby improvement of S/N ratio remains insignificant.
It has been mentioned that the reset noise is eliminated by the clamp circuit 51. However, in many of actual applications, the signal portion is held additionally by a sample and hold circuit 55 before being outputted, as is shown in FIG. 7. (In some cases, a sample circuit is used in place of the sample and hold circuit.) In FIGS. 5 and 7, the time constants which determine the rates at which the signal is charged in capacitances C.sub.CP and C.sub.SH of the capacitors 56 and 57 in the clamp circuit 51 and the sample and hold circuit 55, respectively, are selected usually to be several nanoseconds which is sufficiently small as compared with the period of the clock pulse driving the solid-state imager, which period is 140 nsec when the frequency of the clock pulse signal is 7.2 MHz. For this reason, the capacities C.sub.CP and C.sub.SH of the capacitors 56 and 57 in the clamp circuit 51 and the sample and hold circuit 55 are usually dimensioned on the order of about 20 to 30 pF, respectively. However, in the circuit arrangements shown in FIGS. 5 and 7, the clamp circuit 51 and the sample and hold circuit 55 themselves produce noise having relatively high noise level. Thus, the improvement factor of the S/N ratio remains small. It is noted that the noise produced by a transistor 56' and a junction FET 57' among others is at a significantly high level.